Data Switching and Distribution

Tel Data System GmbH is representing, Telspan Data ruggedized switches and distribution products for use in the

Ruggedized Switches

iES are managed switches & gateways w/ FPGAs for data processing, protocol transforms & CH7/HDLC PCM encoding/decoding of ethernet traffic.

iES-6

6 Port Layer 2/3 Managed Switch with end node timing and discrete signal capabilities

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Highlights
• (6) Tri-Speed Ports w/ Layer 2/3 Switch Management
• IRIG-A/B/G Time Code Generator
• (1) IRIG DC Input, (2) IRIG DC/1PPS Outputs & (2) IRIG AM Outputs
• (1-4) Hardware IEEE-1588v2 Clocks
• Programmable Discrete Inputs/Output

Overview

The iES-6 integrated Ethernet Switch, is a rugged 6 port layer 2/3 managed gigabit Ethernet switch with end node timing & discrete signal capabilities for demanding test instrumentation environments on airborne, shipboard or mobile ground vehicles.
Programmable discrete outputs can be used to control end node devices, on or off the network, as well as
feedback into the iES-6 from discrete inputs.
iES-6 contains a hardware based IEEE-1588v2 time engine with (4) independent clocks which can be setup as ordinary, boundary, peer to peer transparent or end to end transparent, master only, slave only & one or two step clock. A Grand Master clock capability is available on the iES-12 & iES-16. The hardware timer in the MAC, provides (20) nanosecond accuracy & (4) nanosecond resolution.
The iES-6 contains a Content-Aware Packet Processor for wire speed packet inspection of advanced VLAN & QoS classifications/manipulations, IP source guarding, & security features. These are just a few of the types of inspections which can be performed. Selected ingress traffic can be applied across the iES-6 or per port. There are several methods of configuring traffic filtering, port use limit control, VLAN/MAC address, packet/rate limiters, port based & frame type. Overview The iES-6 integrated Ethernet Switch, is a rugged 6 port layer 2/3 managed gigabit Ethernet switch with end
node timing & discrete signal capabilities for demanding test instrumentation environments on airborne,
shipboard or mobile ground vehicles.
Programmable discrete outputs can be used to control end node devices, on or off the network, as well as
feedback into the iES-6 from discrete inputs.
iES-6 contains a hardware based IEEE-1588v2 time engine with (4) independent clocks which can be setup as ordinary, boundary, peer to peer transparent or end to end transparent, master only, slave only & one or two step clock. A Grand Master clock capability is available on the iES-12 & iES-16. The hardware timer in the MAC, provides (20) nanosecond accuracy & (4) nanosecond resolution.
The iES-6 contains a Content-Aware Packet Processor for wire speed packet inspection of advanced VLAN & QoS classifications/manipulations, IP source guarding, & security features. These are just a few of the types of inspections which can be performed. Selected ingress traffic can be applied across the iES-6 or per port. There are several methods of configuring traffic filtering, port use limit control, VLAN/MAC address, packet/rate limiters, port based & frame type.

iES-12

12-Port Layer 2/3 Managed switch & gateway w/FPGA for PCM Encoding/Decoding of Ethernet Traffic

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Highlights

• (12) Tri-Speed Ports w/ Layer 2/3 Management
• Switch Connected FPGA
• 2 PCM – 1 Input, 1 Output (RS-422)
• CH7 / HDLC PCM Encoder & Decoder
• GPS Receiver, IRIG Time Input/Output AM/DC w/ 1PPS
• H/W IEEE-1588 Clocks w/ Grand Master Capability
• Programmable Discrete Inputs/Outputs
• Audio Video Bridging (AVB) capability

Overview

The iES-12 integrated Ethernet Switch, is a rugged 12 port layer 2/3 managed gigabit Ethernet switch with end node timing and discrete signal capabilities for demanding environments on airborne, shipboard & ground vehicles. Acting as a gateway, the iES provides IRIG 106 Chapter 7 PCM conversion which allows the unit to function as an Ethernet-to-telemetry encoder and telemetry-to-Ethernet decoder.
Switch traffic filtering capabilities include; Port User Limit Control, VLAN/ MAC Address (Static MAC Table), Packet/Bit Rate Limiters, Port Based and Frame Type and IP Filtering (ACL, Static/Dynamic Multicast). Audio Video Bridging (AVB) capability is also supported.
A switch connected FPGA provides built-in IRIG 106 Chapter 7 PCM encoding & decoding. This allows PCM output of VLAN, mirrored or filtered Ethernet switch traffic or from the PCM input decoded Ethernet back out the switch Ethernet ports. A programmable FPGA tied directly into the switch with two 1G interfaces provides line-rate packet processing capabilities. Discrete outputs (programmable or data driven) can be used to control end node devices, on or off the network, as well as feedback into the iES-12 from discrete inputs.

With multiple time sources and outputs, the iES-12 provides end node device IRIG time signals. iES-12
contains a high accuracy internal GPS receiver & a hardware based IEEE-1588v2 time engine both able to drive the internal IRIG-A/B/G Time Code Generator for time outputs. The IEEE-1588v2 time engine provides  1-4 independent clocks (ordinary, boundary, transparent, 1/2 step, peer-to-peer or end-to-end).

iES-16

12-Port Layer 2/3 Managed switch & gateway w/FPGA for PCM Encoding/Decoding of Ethernet Traffic

 

Please see datasheet for more information. We are please to help you with your project!

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Gateways
Instrumentation Gateway – iGU

Configurable gateway between instrumentation systems, Ethernet networks and telemetry transmitters. Contains a layer 2/3 managed switch, FPGA & quad-core ARM CPU for data processing & protocol transforms

Features

• PCM Inputs/Outputs, NTSC Video Input
• IEEE-1588v2 Master/Slave, IRIG TCG
• Ethernet & NTSC Video to Chapter 10
• Ethernet & Chapter 10 Encoding to Chapter 7/HDLC PCM
• Chapter 7/HDLC PCM Decoding to Ethernet & CH10

Switches
Integrated Ethernet Switches – iES-16/12/8/6 are layer 2/3

managed gigabit Ethernet switches w/ end-node timing for demanding test instrumentation environments

Features

• IRIG 106 Chapter 7/HDLC PCM Encoder/Decoder
• IRIG-A/B/G Time Code Generator (GPS/PTP Source)
• IEEE-1588 PTP Clocks w/ Grand Master (GPS Source)
• IRIG DC/AM/1PPS Outputs
• Programmable Discrete Inputs/Outputs
• iES-12 & iES-16 contain a Switch Connected FPGA for Packet Level Data Processing

TAP’s
Remote TAP & Aggregation Gateway – RTAG

Based on the MITRs Tap & Interface Modules (TIM), the RTAG provides a distributed “TAP & Aggregate” capability for copper and optical links on an existing platform

Features

• Ethernet, Fibre Channel & IEEE-1394/AS5643 TAP’s
• Optical & Copper
• Rx/Tx TAP to Tx Output or Aggregate Multiple TAP’s to Tx Output
• Fibre to Copper Media Converter
• S-Group Message Filtering
• Chapter 7/HDLC PCM Encoder/Decoder